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| R Technical Data XC5200 Logic Cell Array Family Preliminary (v1.0) * April 1995 and XACT are registered trademarks of Xilinx. All XCprefix product designations, XACT-Performance, X-BLOX, XChecker, XDM, LCA, Logic Cell, Express, VersaBlock, and VersaRing are trademarks of Xilinx. The Programmable Logic Company and The Programmable Gate Array Company are service marks of Xilinx. Mentor is a registered trademark and NETED, Design Architect, QuickSim, and QuickSim II are trademarks of Mentor Graphics, Inc. OrCAD is a registered trademark of OrCAD Systems Corporation. Viewlogic, Viewsim, and Viewdraw are registered trademarks of Viewlogic Systems, Inc. Synopsys is a registered trademark of Synopsys, Inc. Xilinx does not assume any liability arising out of the application or use of any product described herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx devices and products are protected under one or more of the R following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,783,607; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,267,187; 5,224,056; 5,245,277; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; RE 34,363; RE 34,444; and RE 34,808. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third-party right. Xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. R TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 XC5200 Family Compared to XC4000 Family . . . . . . . . . . . . . . . . . . . . . . . . . 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VersaBlock Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 R XC5200 Logic Cell Array Family Product Description * Fully supported by XACT(R) Development System -- Includes complete support for XACT-PerformanceTM, X-BLOXTM, Unified Libraries, Relationally Placed Macros (RPMs), XDelay, and XCheckerTM -- Wide selection of PC and workstation platforms -- Interfaces to more than 100 third-party CAE tools Preliminary (v1.0) Features * High-density family of Field-Programmable Gate Arrays (FPGAs) * Design- and process-optimized for low cost -- 0.6-m three-layer metal (TLM) process * System performance up to 50 MHz * SRAM-based, in-system reprogrammable architecture * Flexible architecture with abundant routing resources -- VersaBlockTM logic module -- VersaRingTM I/O interface -- Dedicated cell-feedthrough path -- Hierarchical interconnect structure -- Extensive registers/latches -- Dedicated carry logic for arithmetic functions -- Cascade chain for wide input functions -- Dedicated IEEE 1149.1 boundary-scan logic -- Internal 3-state bussing capability -- Four global low-skew clock or signal distribution nets -- Globally selectable CMOS or TTL input thresholds -- Output slew-rate control -- 8-mA sink current per output * Configured by loading binary file -- Unlimited reprogrammability -- Six programming modes, including high-speed ExpressTM mode * 100% factory tested * 100% footprint compatibility for common packages Table 1. Device Typical Gate Range VersaBlock Array Number of CLBs Number of Flip-Flops Number of I/Os TBUFs per Horizontal Longline Description The XC5200 Field-Programmable Gate Array Family is engineered to deliver the lowest cost of any FPGA family. By optimizing the new XC5200 architecture for TLM technology and 0.6-m CMOS SRAM process, dramatic advances have been made in silicon efficiency. These advances position the XC5200 family as a cost-effective, high-volume alternative to gate arrays. Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a robust feature set to high-density programmable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5200 family is delivered through the familiar XACT software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, and synthesis. Designers utilizing logic synthesis can use their existing Synopsys, Viewlogic, Mentor, and Exemplar tools to design with the XC5200 devices. Initial XC5200 Field-Programmable Gate Array Family Members XC5202 2,200 2,700 8x8 64 256 84 10 XC5204 3,900 4,800 10 x 12 120 480 124 14 XC5206 6,000 7,500 14 x 14 196 784 148 16 XC5210 10,000 12,000 18 x 18 324 1,296 196 20 XC5215 14,000 18,000 22 x 22 484 1,936 244 24 1 XC5200 Logic Cell Array Family Preliminary (v1.0) * XC5200 devices have no dedicated wide edge decoders. The XC5200 carry logic, unlike the XC4000 architecture, can be used to cascade function generators to implement wide AND and OR functions, for example. * The XC5200 family contains a flexible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the Configurable Logic Block (CLB), a Local Interconnect Matrix (LIM), and direct connects to neighboring VersaBlocks. * XC5200 CLBs are roughly equivalent to two XC4000 CLBs. Each XC5200 CLB contains four 4-input function generators and four registers, which are configured as four independent Logic CellsTM (LCs). The output from each function generator can be brought out as a CLB output and/or drive the D input of a flip-flop. Pairs of logic cells can be combined to form a 5-input function generator. * There are four direct feedthrough paths per CLB, one per LC. These paths can provide extra data input lines or serve as local routes without consuming any logic resources. * The XC5200 family has a global reset, whereas the XC4000 family has both a global set and a global reset. * Unlike the XC4000 family, each register can be configured as either an edge-triggered D flip-flop or a transparent, level-sensitive latch. * There are no dedicated IOB flip-flops, but there are fast direct connects to adjacent CLBs. XC5200 Family Compared to XC4000 Family For those readers already familiar with the XC4000 family of Xilinx Field-Programmable Gate Arrays, here is a concise description of the similarities and differences between the XC4000 and XC5200 families. Superficially, the XC5200 family is quite similar to the XC4000 family. Both use CMOS SRAM technology. Both use 4-input lookup tables with unshared inputs. Both have a dedicated fast carry track, and dedicated boundary-scan logic in the input/output blocks (IOBs). XC5200 and XC4000 devices are footprint and pin-out compatible; their pin names and pin locations are identical. XC5200 devices offer the same configuration options as XC4000 devices, and they can be intermixed with XC4000 devices in a configuration daisy chain. There are also, however, significant differences between the two families: * XC5200 lookup tables cannot be used as RAM. * The XC5200 family offers dedicated carry logic, but differs from the XC4000 family in that the sum is generated in an additional function generator in the adjacent column. An XC5200 device thus uses twice as many function generators for adders, subtracters, accumulators, and some counters. Note, however, that a loadable up/down counter requires the same number of function generators in both families. Table 2. Four Generations of Xilinx Field-Programmable Gate Array Families XC5200 4 20 12 4 no no yes yes yes yes yes no no XC4000 3 9 4 8 yes yes no yes yes yes yes no no XC3000A/XC3100A 2 5 2 2 no no no no yes no yes yes yes XC2000 2 4 2 2 no no no no no no no yes yes Parameter Function generators per CLB Logic inputs per CLB Logic outputs per CLB Low-skew global buffers User RAM Dedicated decoders Cascade chain Fast carry logic Internal 3-state drivers IEEE boundary scan Output slew-rate control Power-down option Crystal oscillator circuit 2 R Table 3. Routing Resource Comparison XC5200 10 4 8 8 yes XC4000 8 4 6 0 no Architectural Overview Figure 1 presents a simplified, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, programmable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks. General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM). VersaBlock: Abundant Local Routing Plus Versatile Logic The basic logic element in each VersaBlock structure is the Logic Cell, shown in Figure 2. Each LC contains a 4input function generator (F), a storage device (FD), and control logic. There are five independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC. Each Logic Cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register; this feature is a first for FPGAs. The storage device is configurable as either a D flip-flop or a latch. The control logic consists of carry logic for fast implementation of arithmetic functions, which can also be configured as a cascade chain allowing decode of very wide input functions. The XC5200 CLB consists of four LCs, as shown in Figure 3. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be configured to implement 5-input functions. The challenge of FPGA implementation software has always been to maximize the usage of logic resources. The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect -- the LIM and direct connects. These two interconnect resources, combined with the CLB, form the VersaBlock, represented in Figure 4. Resource Single-length Lines Double-length Lines Longlines Direct Connects VersaRing * The TLM process allows significant improvements in the routing structure. Each XC5200 VersaBlock element has complete intra-CLB routing, the LIM, and offers four direct routing connections to each of the four neighboring CLBs (North, South, East, and West). Any function generator or flip-flop thus has unrestricted connectivity to 19 other function generators or flipflops: three in its own CLB, and 16 in the adjacent CLBs. These direct connects do not compete with the general routing resources (see Table 3). * Each XC5200 3-state buffer (TBUF) can drive up to two horizontal Longlines; each XC4000 TBUF accesses only one horizontal Longline. * There is a special racetrack, the VersaRing, between the outer edge of the core CLB array and the ring of IOBs, providing significant help in overcoming the problems caused by early locking of I/O pins. * There are no internal pull-ups for XC5200 Longlines. Input/Output Blocks (IOBs) VersaRing GRM VersaBlock GRM VersaBlock GRM VersaBlock CO VersaRing GRM VersaBlock GRM VersaBlock GRM VersaBlock VersaRing DO DI D Q GRM VersaBlock GRM VersaBlock GRM VersaBlock F4 F3 F2 F1 FD F X VersaRing X4955 CI CE CK CLR X4956 Figure 1. XC5200 Architectural Overview Figure 2. XC5200 Logic Cell (Four LCs per CLB) 3 XC5200 Logic Cell Array Family Preliminary (v1.0) LC3 DI CO DO D Q GRM 24 24 TS 4 4 F4 F3 F2 F1 FD F X CLB LC3 4 4 4 LC2 LC1 LC0 4 4 LC2 DO DI D F4 F3 F2 F1 X Q FD F 4 4 LIM Direct Connects Figure 4. VersaBlock X5707 LC1 DO DI D F4 F3 F2 F1 X Q FD F The LIM provides 100% connectivity of the inputs and outputs of each LC in a given CLB. The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes. The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general interconnect. These two layers of local routing resource improve the granularity of the architecture, effectively making the XC5200 family a "sea of logic cells." Each VersaBlock has four 3-state buffers that share a common enable line and directly drive horizontal Longlines, creating robust on-chip bussing capability. The VersaBlock allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion. These resources also minimize local routing congestion and improve the efficiency of the general interconnect, which is used for connecting larger groups of logic. It is this combination of both fine-grain and coarse-grain architecture attributes that maximize logic utilization in the XC5200 family. This symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions. LC0 DO DI D F4 F3 F2 F1 X CI CE CK CLR X4957 Q FD F Figure 3. Configurable Logic Block 4 R VersaRing I/O Interface The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the I/O-togate ratio and decreasing the cost per I/O. A "freeway" of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement flexibility. These incremental edge resources give users increased flexibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manufactured concurrent with the logic design. General Routing Matrix The GRM is functionally similar to the switch matrices found in other architectures, but it is novel in its tight coupling to the logic resources contained in the VersaBlocks. Advanced simulation tools were used during the development of the XC5200 architecture to determine the optimal level of routing resources required. The XC5200 family contains six levels of interconnect hierarchy -- a series of single-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained within each VersaBlock. Throughout the XC5200 interconnect, an efficient multiplexing scheme, in combination with TLM, was used to improve the overall efficiency of silicon usage. Performance Overview The XC5200 family has been benchmarked with many designs running synchronous clock rates up to 40 MHz. The performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the interconnect routing. Table 4 shows some performance numbers for representative circuits, using worst-case timing parameters for the Engineering Sample (ES) speed grade. A rough estimate of timing can be made by assuming 6 ns per logic level, which includes direct-connect routing delays. More accurate estimations can be made using the information in the Switching Characteristic Guideline section. Table 4. Performance for Several Common Circuit Functions XC5200 Speed Grade Function -6 16-bit Decoder from Input Pad 24-bit Accumulator 16-to-1 Multiplexer 16-bit Unidirectional Loadable Counter 16-bit U/D Counter 16-bit Adder 24-bit Loadable U/D Counter 9 ns 32 MHz 16 ns 40 MHz 40 MHz 24 ns 36 MHz -5 8 ns 39 MHz 13 ns 50 MHz 50 MHz 20 ns 42 MHz -4 5 XC5200 Logic Cell Array Family Preliminary (v1.0) Xilinx offers XACT development system interfaces to the following design environments: * Viewlogic Systems (Viewdraw, Viewsim) * Mentor Graphics V8 (NETED, QuickSim, Design Architect, QuickSim II) * OrCAD (SDT, VST) Development System The powerful features of the XC5200 device family require an equally powerful, yet easy-to-use, set of development tools. Xilinx provides an enhanced version of the Xilinx Automatic CAE Tools (XACT), optimized for the XC5200 family. As with other logic technologies, the basic methodology for XC5200 FPGA design consists of three interrelated steps: design entry, implementation, and verification. Popular generic tools are used for entry and simulation (for example, Viewlogic Systems's Viewdraw schematic editor and Viewsim simulator), but architecture-specific tools are needed for implementation. All Xilinx development system software is integrated under the Xilinx Design Manager (XDMTM), providing designers with a common user interface regardless of their choices of entry and verification tools. XDM simplifies the selection of command-line options with pull-down menus and online help text. Application programs ranging from schematic capture to Partitioning, Placement, and Routing (PPR) can be accessed from XDM, while the program-command sequence is generated and stored for documentation prior to execution. The XMAKE command, a design compilation utility, automates the entire implementation process, automatically retrieving the design's input files and performing all the steps needed to create configuration and report files. Several advanced features of the XACT system facilitate XC5200 FPGA design. RPMs -- schematic-based macros with relative location constraints to guide their placement within the FPGA -- help to ensure an optimized implementation for common logic functions. An abundance of local routing permits RPMs to be contained within a single VersaBlock or to span across multiple VersaBlocks. XACT-Performance allows designers to enter the exact performance requirements during design entry, at the schematic level, to guide PPR. Design Entry Designs can be entered graphically, using schematiccapture software, or in any of several text-based formats (such as Boolean equations, state-machine descriptions, and high-level design languages). Xilinx and third-party CAE vendors have developed library and interface products compatible with a wide variety of design-entry and simulation environments. A standard interface-file specification, Xilinx Netlist File (XNF), is provided to simplify file transfers into and out of the XACT development system. * Synopsys (Design Compiler, FPGA Compiler) * Xilinx-ABEL (State Machine module generator) * X-BLOX (Graphical Mode Generator) Many other environments are supported by third-party vendors. Currently, more than 100 packages are supported. The unified schematic library for the XC5200 FPGA reflects the wide variety of logic functions that can be implemented in these versatile devices. The library contains over 400 primitives and macros, ranging from 2input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. Designing with macros is as easy as designing with standard SSI/MSI functions. The "soft macro" library contains detailed descriptions of common logic functions, but does not contain any partitioning or routing information. The performance of these macros depends, therefore, on how the PPR software processes the design. RPMs, on the other hand, do contain predetermined partitioning and relative placement information, resulting in an optimized implementation for these functions. Users can create their own library elements -- either soft macros or RPMs -- based on the macros and primitives of the standard library. The X-BLOX design language is a graphics-based highlevel description language (HDL) that allows designers to use a schematic editor to enter designs as a set of generic modules. The X-BLOX compiler synthesizes and optimizes the modules for the target device architecture, automatically choosing the appropriate architectural resources for each function. The XACT design environment supports hierarchical design entry, with top-level drawings defining the major functional blocks, and lower-level descriptions defining the logic in each block. The implementation tools automatically combine the hierarchical elements of a design. Different hierarchical elements can be specified with different design entry tools, allowing the use of the most convenient entry method for each portion of the design. 6 R Design Implementation The design implementation tools satisfy the requirements for an automated design process. Logic partitioning, block placement, and signal routing are performed by the PPR program. The partitioner takes the logic from the entered design and maps the logic into the architectural resources of the FPGA (such as the logic blocks, I/O blocks, and 3state buffers). The placer then determines the best locations for the blocks, depending on their connectivity and the required performance. The router finally connects the placed blocks together. The PPR algorithms support fully automatic implementation of most designs. However, for demanding applications, the user may exercise various degrees of control over the automated implementation process. Optionally, user-designated partitioning, placement, and routing information can be specified as part of the designentry process. The implementation of highly structured designs can benefit greatly from the basic floorplanning techniques familiar to designers of large gate arrays. The PPR program includes XACT-Performance, a feature that allows designers to specify the timing requirements along entire paths during design entry. Timing path analysis routines in PPR then recognize and accommodate the user-specified requirements. Timing requirements can be entered on the schematic in a form directly relating to the system requirements (such as the targeted minimum clock frequency, or the maximum allowable delay on the data path between two registers). So, while the timing of each individual net is not predictable, the overall performance of the system along entire signal paths is automatically tailored to match usergenerated specifications. Design Verification The high development cost associated with common mask-programmed gate arrays necessitates extensive simulation to verify a design. Due to the custom nature of masked gate arrays, mistakes or last-minute design changes cannot be tolerated. A gate-array designer must simulate and test all logic using simulation software. Simulation describes what happens in a system under worst-case situations. However, simulation can be tedious and slow, and simulation vectors must be generated. A few seconds of system time can take weeks to simulate. Programmable-gate-array users, however, can use incircuit debugging techniques in addition to simulation. Because Xilinx devices are reprogrammable, designs can be verified in real time without the need for extensive simulation vectors. The XACT development system supports both simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database. This data can then be sent to the simulator to verify timing-critical portions of the design database using XDELAY, the Xilinx static timing analyzer tool. Back-annotation -- the process of mapping the timing information back into the signal names and symbols of the schematic -- eases the debugging effort. For in-circuit debugging, the XACT development system includes a serial download and readback cable (XChecker) that connects the FPGA in the system to the PC or workstation through an RS232 serial port. The engineer can download a design or a design revision into the system for testing. The designer can also single-step the logic, read the contents of the numerous flip-flops on the device, and observe internal logic levels. Simple modifications can be downloaded into the system in a matter of minutes. 7 XC5200 Logic Cell Array Family Preliminary (v1.0) Detailed Functional Description CLB Logic Figure 3 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a D-Type flip-flop or latch with common clock, clock enable, and clear, but individually selectable clock polarity. Additional logic features provided in the CLB are: * High-speed carry propagate logic. * High-speed pattern decoding. * High-speed direct connection to flip-flop D-inputs. * Each flip-flop can be programmed individually as either a transparent, level-sensitive latch or a D flip-flop. * Four 3-state buffers with a shared Output Enable. * Two 4-input LUTs can be combined to form an independent 5-input LUT. 5-Input Functions Figure 5 illustrates how the outputs from the LUTs from LC0 and LC1 can be combined with a 2:1 multiplexer (F5_MUX) to provide a 5-input function. The outputs from the LUTs of LC2 and LC3 can be similarly combined. CO DI D FD I1 I2 I3 I4 F4 F3 F2 F1 DO Q F X LC1 F5_MUX DO I5 DI D FD F4 F3 F2 F1 Q out Qout F CI CE CK CLR X LC0 X5710 5-Input Function Figure 5. Two LUTs in Parallel Combined to Create a 5-input Function 8 R Carry Function The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) symbol on a schematic is used to indicate the XC5200 carry logic. This symbol represents the dedicated 2:1 multiplexer in each LC that performs the one-bit highspeed carry propagate per logic cell (four bits per CLB). While the carry propagate is performed inside the LC, an adjacent LC must be used to complete the arithmetic function. Figure 6 represents an example of an adder function. The carry propagate is performed on the CLB shown, which also generates the half-sum for the four-bit adder. An adjacent CLB is responsible for XORing the half-sum with the corresponding carry-out. Thus an adder or counter requires two LCs per bit. Notice that the carry chain requires an initialization stage, which the XC5200 family accomplishes using the carry initialize (CY_INIT) macro and one additional LC. The XC5200 library contains a set of RPMs and arithmetic functions designed to take advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement customized RPMs, freeing the designer from the need to become an expert on architectures. carry out A3 or B3 CO DI DO D Q FD carry3 DI CO DO D F4 F3 F2 F1 Q FD A3 and B3 to any two F4 F3 F2 F1 CY_MUX XOR XOR X sum3 X half sum3 LC3 A2 or B2 DI LC3 DI DO DO carry2 D Q FD D F4 F3 F2 F1 Q FD A2 and B2 to any two F4 F3 F2 F1 CY_MUX XOR X half sum2 XOR X sum2 LC2 A1 or B1 DI LC2 DI DO DO carry1 D Q FD D F4 F3 F2 F1 Q FD A1 and B1 to any two F4 F3 F2 F1 CY_MUX XOR X half sum1 XOR X sum1 LC1 A0 or B0 DI LC1 carry0 DI DO DO D Q FD D F4 F3 F2 F1 Q FD A0 and B0 to any two F4 F3 F2 F1 CY_MUX XOR X CI CE CK CLR half sum0 XOR X CI CE CK CLR sum0 LC0 LC0 0 carry in CY_MUX F=0 Initialization of carry chain (One Logic Cell) X5709 Figure 6. XC5200 CY_MUX Used for Adder Carry Propagate 9 XC5200 Logic Cell Array Family Cascade Function Each CY_MUX can be connected to the CY_MUX in the adjacent LC to provide cascadable decode logic. Figure 7 illustrates how the 4-input function generators can be configured to take advantage of these four cascaded Preliminary (v1.0) CY_MUXes. Note that AND and OR cascading are specific cases of a general decode. In AND cascading all bits are decoded equal to logic one, while in OR cascading all bits are decoded equal to logic zero. The flexibility of the LUT achieves this result. cascade out CO DI DO out D A15 A14 A13 A12 F4 F3 F2 F1 AND CY_MUX Q FD X LC3 DI D CY_MUX A11 A10 A9 A8 DO Q FD F4 F3 F2 F1 AND X LC2 DI DO D A7 A6 A5 A4 F4 F3 F2 F1 AND CY_MUX Q FD X LC1 DI DO D A3 A2 A1 A0 F4 F3 F2 F1 CI cascade in CE CK CLR AND CY_MUX Q FD X LC0 CY_MUX F=0 Initialization of carry chain (One Logic Cell) X5708 Figure 7. XC5200 CY_MUX Used for Decoder Cascade Logic 10 R 3-State Buffers The XC5200 family has four dedicated TBUFs per CLB. The four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. When in 3-state mode the CLB's output enable (TS) control signal drives the enable to all four buffers (see Figure 8). Each TBUF can drive up to two horizontal Longlines Oscillator Start-Up On start-up, all XC5200 internal flip-flops are reset. The XC5200 devices do not support the "INIT=" attribute. Thus, the XC5200 family has only a global reset (GR) signal. The user can assign the pin location for the GR signal and use it to reset asynchronously all of the flipflops in the design without using general routing resources. The user can also assign a positive or negative polarity to GR. Boundary Scan The XC5200 oscillator (OSC52) divides the internal 16MHz clock or a user clock that is connected to the "C" pin. The user then has the choice of dividing by 4, 16, 64, or 256 for the "OSC1" output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the "OSC2" output. The division is specified via a "DIVIDEn_BY=x" attribute on the symbol, where n=1 for OSC1, or n=2 for OSC2. The OSC5 macro is used where an internal oscillator is required. The CK_DIV macro is applicable when a user clock input is specified (see Figure 9). XC5200 devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP can also support two USERCODE instructions. Boundary-scan operation is independent of individual IOB configuration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability after configuration provides flexibility for interconnect testing. Also, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This technique partially compensates for the lack of INTEST support. The public boundary-scan instructions are always available prior to configuration. After configuration, the public instructions and any USERCODE instructions are only available if specified in the design. While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the Logic Cell Array (LCATM) device, and to read back the configuration data. All of the XC4000 boundary-scan modes are supported in the XC5200 family. Three additional outputs for the User Register are provided (Reset, Update, and Shift), representing the decoding of the corresponding state of the boundary-scan internal state machine. For details on boundary scan, refer to "Boundary Scan in XC4000 Devices -- Application Note" on pages 8-45 through 8-42 of the 1994 Xilinx Programmable Logic Data Book. TS CLB CLB LC3 LC2 LC1 LC0 Horizontal Longlines X5706 Figure 8. XC5200 3-State Buffer OSC5 OSC1 OSC2 OSC1 OSC2 CK_DIV CLK Figure 9. XC5200 Oscillator Macros 11 XC5200 Logic Cell Array Family Preliminary (v1.0) Direct Connects The unidirectional direct-connect segments are connected to the logic input/output pins through the CLB's input and output multiplexer array, and thus bypass the programmable routing matrix altogether. These lines are intended to increase the routing channel utilization where possible, while simultaneously reducing the delay incurred in speed-critical connections. The direct connects also provide a high-speed path from the edge CLBs to the VersaRing input/output buffers, and thus reduce set-up time, clock-to-out, and combinational propagation delay. The direct connects are ideal for developing customized RPM cells. Using direct connects improves the macro performance, and leaves the other routing channels intact for improved routing. Direct connects can also route through a CLB using one of the four cell-feedthrough paths. VersaBlock Routing Local Interconnect Matrix The GRM connects to the VersaBlock via 24 bidirectional ports (M0-M23). Excluding direct connections, global nets, and 3-statable Longlines, all VersaBlock inputs and outputs connect to the GRM via these 24 ports. Four 3statable unidirectional signals (TQ0-TQ3) drive out of the VersaBlock directly onto the horizontal Longlines. Two horizontal global nets (GH0 and GH1) and two vertical global nets (GV0 and GV1) connect directly to every CLB clock pin; they can connect to other CLB inputs via the GRM. Each CLB also has four unidirectional direct connects to each of its four neighboring CLBs. These direct connects can also feed directly back to the CLB (see Figure 10). In addition, each CLB has 16 direct inputs, four direct connections from each of the neighboring CLBs. These direct connections provide high-speed local routing that bypasses the GRM. The 13 CLB outputs (12 LC outputs plus a Vcc/GND signal) connect to the eight VersaBlock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. Of the eight VersaBlock outputs, four signals drive each neighboring CLB directly, and provide a direct feedback path to the input multiplexers. The four remaining multiplexer outputs can drive the GRM through four TBUFs (TQ0-TQ3). All eight multiplexer outputs can connect to the GRM through the bidirectional M0-M23 signals. All eight signals also connect to the input multiplexers and are potential inputs to that CLB. CLB inputs have several possible sources: the 24 signals from the GRM, 16 direct connections from neighboring VersaBlocks, four signals from global, low-skew buffers (GH0, GH1, GV0, and GV1), and the four signals from the CLB output multiplexers. Unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given CLB input. The flexibility of LUT input swapping and LUT mapping compensates for this limitation. For example, if a 2-input NAND gate is required, it can be mapped into any of the four LUTs, and use any two of the four inputs to the LUT. 12 R To GRM M0-M23 24 8 Global Nets 4 TS COUT 4 4 To Longlines and GRM TQ0-TQ3 North South East West 4 CLB 4 5 4 4 LC3 LC2 LC1 LC0 3 Input Multiplexers 5 3 VCC /GND 3 Output Multiplexers 8 4 4 Direct to East 5 5 Direct North CLK 4 Feedback 4 CE CLR CIN 3 Direct West 4 4 Direct South X5724 Figure 10. VersaBlock Details 13 XC5200 Logic Cell Array Family Preliminary (v1.0) each CLB, and are driven by similar buffers at the periphery of the array from the VersaRing I/O Interface. Bus-oriented microprocessor designs are accommodated by using horizontal Longlines in conjunction with the 3state buffers in the CLB and in the VersaRing. Additionally, programmable keeper cells at the periphery can be enabled to retain the last valid logic level on the Longlines when all buffers are in 3-state mode. Longlines connect to the single-length or double-length lines, or to the logic inside the CLB, through the General Routing Matrix. The only manner in which a Longline can be driven is through the four 3-state buffers; therefore, a Longline-to-Longline or single-line-to-Longline connection through PIPs in the General Routing Matrix is not possible. Again, as a general rule, long- and global-line connections to the General Routing Matrix are unidirectional, with the signal direction from these lines toward the routing matrix. The XC5200 family has no pull-ups on the ends of the Longlines sourced by TBUFs. Consequently, wired functions (i.e., WAND and WORAND) and wide multiplexing functions requiring pull-ups for undefined states (i.e., bus applications) must be implemented in a different way. In the case of the wired functions, the same functionality can be achieved by taking advantage of the carry/cascade logic described above, implementing a wide logic function in place of the wired function. In the case of 3-state bus applications, the user must insure that all states of the multiplexing function are defined. This process is as simple as adding an additional TBUF to drive the bus High when the previously undefined states are activated. Global Clock Buffers Global buffers in Xilinx FPGAs are special buffers that drive a dedicated routing network called Global Lines, as shown in Figure 12. This network is intended for high-fanout clocks or other control signals, to maximize speed and minimize skewing while distributing the signal to many loads. The XC5200 family has a total of four global buffers (BUFG symbol in the library), each with its own dedicated routing channel. Two are distributed vertically and two horizontally throughout the LCA. General Routing Matrix The General Routing Matrix, shown in Figure 11, provides flexible bidirectional connections to the Local Interconnect Matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. A programmable interconnect point (PIP) establishes an electrical connection between two wire segments. The PIP, consisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirectional) connection between two adjoining wires. A collection of PIPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments. A hierarchy of PIPs and associated routing segments combine to provide a powerful interconnect hierarchy: * Forty bidirectional single-length segments per CLB provide ten routing channels to each of the four neighboring CLBs in four directions. * Sixteen bidirectional double-length segments per CLB provide four routing channels to each of four other (nonneighboring) CLBs in four directions. * Eight horizontal and eight vertical bidirectional Longline segments span the width and height of the chip, respectively. * Two low-skew horizontal and vertical unidirectional global-line segments span each row and column of the chip, respectively. Single- and Double-Length Lines The single- and double-length bidirectional line segments make up the bulk of the routing channels. The doublelength lines hop across every other CLB to reduce the propagation delays in speed-critical nets. Regenerating the signal strength is recommended after traversing three or four such segments. XACT place-and-route software automatically connects buffers in the path of the signal as necessary. Single- and double-length lines cannot drive onto Longlines and global lines; Longlines and global lines can, however, drive onto single- and double-length lines. As a general rule, Longline and global-line connections to the programmable routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. Longlines Longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. Row and column splitter PIPs in the middle of the array effectively double the total number of Longlines by electrically dividing them into two separated half-lines. The horizontal Longlines are driven by the 3-state buffers in 14 R GRM VersaBlock GRM VersaBlock GRM VersaBlock GRM VersaBlock GRM VersaBlock GRM VersaBlock 1 2 GRM VersaBlock GRM VersaBlock GRM VersaBlock 3 4 Six Levels of Routing Hierarchy 1 2 3 4 5 6 LIM Single-length Lines Double-length Lines GRM 24 24 4 4 TS CLB LC3 Direct Connects Longlines and Global Lines Local Interconnect Matrix Logic Cell Feedthrough Path (Contained within each Logic Cell) 4 4 4 LC2 LC1 4 4 6 LC0 LIM 4 4 5 Direct Connects Figure 11. XC5200 Interconnect Structure X4963 15 XC5200 Logic Cell Array Family Global Lines Two pairs of horizontal and vertical global lines provide low-skew clock signals to the CLBs. Global lines are driven by low-skew buffers inside the VersaRing. The global lines provide direct input only to the CLB clock pins. The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals. Four clock input pads at the corners of the chip, as shown in Figure 12, provide a high-speed, low-skew clock network to each of the four global-line buffers. In addition to the dedicated pad, the global lines can be sourced by internal logic. PIPs from several routing channels within the VersaRing, inside the IOI cell, can also be configured to drive the global-line buffers. VersaRing Input/Output Interface The VersaRing, shown in Figure 13, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The VersaRing decouples the pad ring's pitch from the core's pitch. Each VersaRing Cell provides up to four pad-cell connections on one side, and connects directly to the CLB ports on the other side. Depending on placement and padcell pitch, any number of pad cells to a maximum of four can be connected to a VersaRing cell. Note: there are no direct connects from the Pads on top and bottom edges. GRM GRM Preliminary The input buffer has globally selected CMOS and TTL input thresholds. The input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip set-up and hold times. Minimum ESD protection is 5 KV using the Human Body Model. VersaRing 8 8 2 2 10 2 Pad Pad 2 8 Interconnect 4 4 Pad Pad VersaBlock 8 2 2 10 8 Pad Pad Input/Output Pad 4 Interconnect Pad VersaBlock 4 2 8 2 8 X5705 The I/O pad, shown in Figure 14, consists of an input buffer and an output buffer. The output driver is an 8-mA full-rail CMOS buffer with 3-state control. Two slew-rate control modes are supported to minimize bus transients. Both the output buffer and the 3-state control are invertible. Pad Figure 13. VersaRing I/O Interface GCK1 GCK4 Vcc I PAD O T GCK2 GCK3 X5704 X4964 Figure 12. Global Lines Figure 14. XC5200 I/O Block 16 R Configuration Configuration is the process of loading design-specific programming data into one or more LCA devices to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Each configuration bit defines the state of a static memory cell that controls either a function LUT bit, a multiplexer input, or an interconnect pass transistor. The XACT development system translates the design into a netlist file. It automatically partitions, places, and routes the logic and generates the configuration data in PROM format. Modes The XC5200 family has seven modes of configuration, selected by a 3-bit input code applied to the LCA mode pins (M0, M1, and M2). There are three self-clocking Master modes, two Peripheral modes, a Slave serial mode, and a new high-speed Slave parallel mode called the Express. See Table 5. Brief descriptions of the seven modes are provided below. For details on all modes except Express, see pages 2-32 through 2-41 of the 1994 Xilinx Programmable Logic Data Book. into the LCA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, to be compatible with different microprocessor addressing conventions. The Master Serial Mode generates CCLK and receives the configuration data in serial form from configuration data in serial form from a Xilinx serial-configuration PROM. Peripheral Modes The two Peripheral modes accept byte-wide data from a bus. A READY/BUSY status is available as a handshake signal. In the asynchronous mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. In the synchronous mode, an externally supplied clock input to CCLK serializes the data. Slave Serial Mode In the Slave Serial mode, the LCA device receives serialconfiguration data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with parallel DIN inputs so that the devices can be configured simultaneously. Daisy Chaining Multiple devices may be daisy-chained together so that they may be programmed using a single bitstream. The first device in the chain may be set to operate in any mode. All devices except the first device in the chain must be set to operate in Slave Serial mode. All CCLK pins are tied together and the data chain passes from DOUT to DIN of successive devices along the chain. Master Modes The Master modes use an internal oscillator to generate CCLK for driving potential slave devices, and to generate address and timing for external PROM(s) containing the configuration data. Master Parallel (up or down) modes generate the CCLK signal and PROM addresses, and receive byte parallel data, which is internally serialized Table 5. Mode Configuration Modes M2 0 1 1 1 0 1 0 0 M1 0 1 0 1 1 0 1 0 M0 0 1 0 0 1 1 0 1 CCLK output input output output input output input -- Data Bit-Serial Bit-Serial Byte-Wide, 00000 Byte-Wide, 3FFFF Byte-Wide Byte-Wide Byte-Wide -- Master Serial Slave Serial Master Parallel up Master Parallel down Peripheral Synchronous * Peripheral Asynchronous Express Reserved * Peripheral Synchronous can be considered byte-wide Slave Parallel 17 XC5200 Logic Cell Array Family Preliminary +5V M0 M1 M2 M0 M1 M2 To Additional Optional Daisy-Chained Devices CS1 DATA BUS +5V D0-D7 DOUT CS1 D0-D7 DOUT XC5200 5K PROGRAM INIT PROGRAM INIT CCLK Optional Daisy-Chained XC5200 PROGRAM INIT CCLK CCLK X6153 To Additional Optional Daisy-Chained Devices Figure 15. Express Mode Express Mode The Express mode (see Figure 15) is similar to the Slave serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK while byte-wide data is loaded directly into the configuration data shift registers. In this mode the XC5200 family is capable of supporting a CCLK frequency of 10 MHz, which is equivalent to an 80-MHz serial rate, because eight bits of configuration data are being loaded per CCLK cycle. An XC5210 in the Express mode, for instance, can be configured in about 2 ms. The Express mode does not support CRC error checking, but does support constantfield error checking. In the Express configuration mode, an external signal drives the CCLK input(s) of the LCA device(s). The first bytes of parallel configuration data must be available at the D inputs of the LCA devices a short set-up time before each rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. See Figure 16. The Express mode is only supported by the XC5200 family. It may not be used, therefore, when an XC5200 device is daisy-chained with devices from other Xilinx families. If the first device is configured in the Express mode, additional devices may be daisy-chained only if every device in the chain is also configured in the Express mode. CCLK pins are tied together and D7-D0 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). All devices receive and recognize the preamble and length count, but frame data is accepted only when CS1 is High and the device's configuration memory is not already full. The status pin DOUT is pulled LOW two internaloscillator cycles (nominally 1 MHz per cycle) after INIT is recognized as High, and remains Low until the device's configuration memory is full. Then DOUT is pulled High to signal the next device in the chain to accept the configuration data on the D7-D0 bus. How to Delay Configuration After Power-Up For details on how to delay configuration after power-up, refer to page 2-32 of the 1994 Xilinx Programmable Logic Data Book. 18 R CCLK 1 TIC INIT TCD 3 2T DC D0-D7 BYTE 0 BYTE 1 BYTE 2 BYTE 3 Serial Data Out (DOUT) LCA Filled Internal INIT RDY/BUSY CS1 X6154 Description CCLK INIT (High) Setup time required DIN Setup time required DIN Hold time required CCLK High time CCLK Low time CCLK Frequency 1 2 3 Symbol TIC TDC TCD TCCH TCCL FCC Min 5 50 0 50 50 Max Units s ns ns ns ns 10 Preliminary MHz Figure 16. Express Mode Programming Switching Characteristics Format Table 6 describes the XC5200 configuration data stream. Table 7 provides details of the internal configuration data structure. Configuration Sequence Figure 17 illustrates the XC5200 start-up sequence. It is described in detail in the sections below. Clear Internal Logic When reprogramming the XC5200 chip, a contention-free state must be reached before memory initialization can begin. In this state internal control lines sequence activities in the following order: long lines are disabled, output drivers are forced Low, and interconnect lines are discharged. Each of these operations requires one cycle of the 1-MHz Initialization clock. This sequencing is important only when reprogramming, because the contention-free state is immediately entered when configuring from a power-on state. 19 XC5200 Logic Cell Array Family Table 6. Data Type Fill Byte Preamble Length Counter Fill Byte Start Byte Data Frame * Cyclic Redundancy Check or Constant Field Check Fill Nibble Extend Write Cycle Postamble Fill Bytes (30) Legend: (unshaded) (light) (dark) Only once per bitstream Once per data frame Once per device SAMPLE/PRELOAD BYPASS Preliminary Unified XC5200 Bitstream Format Value 11111111 11110010 COUNT(23:0) 11111111 11111110 DATA(N-1:0) CRC(3:0) or 0110 1111 FFFFFF 11111110 FFFF...FF Frame Error No Configuration memory Full Yes Pass Configuration Data to DOUT No Yes Pull INIT Low and Stop Master CCLK Goes Active after 50 to 250 s Boundary Scan Instructions Available: VCC 3V Yes No Generate One Time-Out Pulse of 4 ms PROGRAM = Low Yes EXTEST* SAMPLE/PRELOAD* BYPASS CONFIGURE* (*only when PROGRAM = High) Completely Clear Configuration Memory ~1.3 s per Frame INIT High? if Master Yes Sample Mode Lines No Load One Configuration Data Frame Table 7. Internal Configuration Data Structure PROM Size (bits) 42,448 70,736 106,320 165,520 237,776 Xilinx Serial Prom Needed XC1765 XC1728 XC17128 XC17256 XC17256 EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK CCLK Count Equals Length Count Yes Start-Up Sequence No Device XC5202 XC5204 XC5206 XC5210 XC5215 VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22 F Operational I/O Active X6037 If Boundary Scan is Selected Figure 17. Start-up Sequence Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 8 error check bits + 4 fill bits + 4 extended write bits Number of Frames = (12 x number of Columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit Program Data = (Bits per Frame x Number of Frames) + 48 header bits + 8 postamble bits + 280 fill bits PROM Size = Program Data 20 LDC Output = L, HDC Output = H R Clear Address Registers During this phase the configuration address registers are cleared to ensure that they will contain at most a single token at all times. Prior to memory initialization, the XC5200 device eliminates the possibility of multiple tokens within the address register, as is typically the case when powering on. Power-On Time-Out An internal power-on reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the LCA begin to operate (i.e., performs a write-and-read test of a sample pair of configuration memory bits), the programmable I/O buffers are 3-stated with active high-impedance pull-up resistors. A time-out delay -- nominally 4 ms -- is initiated to allow the powersupply voltage to stabilize. For correct operation the power supply must reach VCC(min) by the end of the timeout, and must not dip below it thereafter. There is no distinction between master and slave modes with regard to the time-out delay. Instead, the INIT line is used to ensure that all daisy-chained devices have completed initialization. Since XC2000 devices do not have this signal, extra care must be taken to guarantee proper operation when daisy-chaining them with XC5200 devices. For proper operation with XC3000 devices, the RESET signal, which is used in XC3000 to delay configuration, should be connected to INIT. If the time-out delay is insufficient, configuration should be delayed by holding the INIT pin Low until the power supply has reached operating levels. During all three phases -- Power-on, Initialization, and Configuration -- DONE is held Low; HDC, LDC, and INIT are active; DOUT is driven; and all I/O buffers are disabled. Configuration The length counter begins counting immediately upon entry into the configuration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz clock oscillator after INIT is recognized before toggling CCLK and feeding the serial bitstream. Configuration will not begin until the internal configuration logic reset is released, which happens two cycles after INIT goes High. A master device's configuration is delayed from 32 to 256 s to ensure proper operation with any slave devices driven by the master device. A preamble field at the beginning of the configuration data stream indicates that the next 24 bits represent the length count. The length count equals the total number of configuration bits needed to load the complete configuration data to all daisy-chained devices. Once the preamble and length-count values have been passed through to the next device in the daisy-chain, DOUT is held High to prevent start bits from reaching any daisychained devices. After fully configuring itself, the device passes serial data to downstream daisy-chained devices via DOUT until the full length count is reached. Errors in the configuration bitstream are checked at the end of a frame of data. The device does not check the preamble or length count for errors. In a daisy-chained configuration, configuration data for downstream devices are not checked for errors. If an error is detected after reading a frame, the ERR pin (also known as INIT) is immediately pulled Low and all configuration activity ceases. However, a master or Peripheral Asynchronous device will continue outputting a configuration clock and incrementing the PROM address indefinitely even though it will never complete configuration. A reprogram or power-on must be applied to remove the device from this state. Initialization This phase clears the configuration memory and establishes the configuration mode. The configuration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 MHz). An opendrain bidirectional signal, INIT, is released when the configuration memory is completely cleared. The device then tests for the absence of an external active-low level on INIT. The mode lines are sampled two internal clock cycles later (nominally 2 s). The master device waits an additional 32 s to 256 s (nominally 64-128 s) to provide adequate time for all of the slave devices to recognize the release of INIT as well. Then the master device enters the Configuration phase. Start-Up and Operation The XC5200 start-up sequence is identical to that of the XC4000 family. Each of these events may occur in any order: (a) DONE is pulled High; and/or (b) user I/Os become active; and/or (c) Internal Reset is deactivated. As a configuration option, the three events may be triggered by a user clock rather than by CCLK, or the startup sequence may be delayed by externally holding the DONE pin Low. In any mode, the clock cycles of the start-up sequence hare not included in the length count. The length of the bitstream is greater than the length count. 21 XC5200 Logic Cell Array Family Preliminary Pin Functions During Configuration CONFIGURATION MODE: SLAVE <1:1:1> MASTER-SER <0:0:0> SYN.PERIPH <0:1:1> TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) TDI TCK TMS M1 (LOW) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (I) TDO TDI TCK TMS M1 (LOW) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) CSO (I) DATA 4 (I) DATA 3 (I) RS (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (O) TDO WS (I) CS1 (I) A16 A17 TDI TCK TMS M1 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) TDO A0 A1 A2 A3 A4 A5 A6 A7 A16 A17 TDI TCK TMS M1 (LOW) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) TDO A0 A1 A2 A3 A4 A5 A6 A7 DIN (I) DOUT CCLK (I) TDO DIN (I) DOUT CCLK (O) TDO A8 A9 A10 A11 A12 A13 A14 A15 Represents a 50-k to 100-k pull-up before and during configuration * INIT is an open-drain output during configuration (I) Represents an input (O) Represents an output A8 A9 A10 A11 A12 A13 A14 A15 GCK1-I/O I/O TDI-I/O TCK-I/O TMS-I/O I/O I/O I/O I/O GCK2-I/O I/O I/O I/O I/O DONE PROGRAM I/O GCK3-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CCLK (I) TDO-I/O I/O GCK4-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ALL OTHERS Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-k to 100-k pull-up resistor. 22 R Pin Descriptions Permanently Dedicated Pins Vcc Eight or more (depending on package type) connections to the nominal +5-V supply voltage. All must be connected. GND Eight or more (depending on package type) connections to ground. All must be connected. CCLK During configuration, Configuration Clock is an output of the LCA in master modes or Asynchronous Peripheral mode, but is an input to the LCA in Slave Serial mode and Synchronous Peripheral mode. After configuration, CCLK has a weak pull-up resistor and can be selected as Readback Clock. DONE This is a bidirectional signal with optional pull-up resistor. As an output, it indicates the completion of the configuration process. The configuration program determines the exact timing, the clock source for the Lowto-High transition, and enable of the pull-up resistor. As an input, a Low level on DONE can be configured to delay the global logic initialization or the enabling of outputs. PROGRAM This is an active-Low input, held Low during configuration, that forces the LCA to clear its configuration memory. When PROGRAM goes High, the LCA executes a complete clear cycle, before it goes into a WAIT state and releases INIT. After configuration, it has an optional pullup resistor. User I/O Pins That Can Have Special Functions RDY/BUSY During peripheral modes, this pin indicates when it is appropriate to write another byte of data into the LCA device. The same status is also available on D7 in Asynchronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, this is a user-programmable I/O pin. RCLK During Master Parallel configuration, each change on the A0-15 outputs is preceded by a rising edge on RCLK, a redundant output signal. After configuration, this is a userprogrammable I/O pin. M0, M1, M2 As mode inputs, these pins are sampled before the start of configuration to determine the configuration mode to be used. After configuration, M0, M1, and M2 become userprogrammable I/O. TDO If boundary scan is used, this is the Test Data Output. If boundary scan is not used, this pin becomes userprogrammable I/O. TDI, TCK, TMS If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs, respectively, coming directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the boundary scan option is not selected, all boundary scan functions are inhibited once configuration is completed. These pins become user-programmable I/O. HDC High During Configuration is driven High until configuration is completed. It is available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable I/O pin. 23 XC5200 Logic Cell Array Family Preliminary Pin Descriptions LDC Low During Configuration is driven Low until configuration completes. It is available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable I/O pin. INIT Before and during configuration, this is a bidirectional signal. An external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the LCA device in the internal WAIT state before the start of configuration. Master-mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After configuration, this is a user-programmable I/O pin. GCK1 - GCK4 Unrestricted User-Programmable I/O Pins Four Global Inputs each drive a dedicated internal global net with short delay and minimal skew. If not used for this purpose, any of these pins is a user-programmable I/O pin. CS0, CS1, WS, RS These four inputs are used in peripheral modes. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer; a Low on Read Strobe (RS) changes D7 into a status output: High if Ready, Low if Busy, and D0...D6 are active Low. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. A0 - A17 During Master Parallel mode, these 18 output pins address the configuration EPROM. After configuration, these are user-programmable I/O pins. I/O A pin that can be configured to be input and/or output after configuration is completed. Before configuration is completed, these pins have an internal high-value pull-up resistor that defines the logical level as High. During Slave Serial or Master Serial configuration modes, this is the serial configuration data input receiving data on the rising edge of CCLK. During parallel configuration modes, this is the D0 input. After configuration, DIN is a user-programmable I/O pin. DOUT During configuration in any mode, this is the serial configuration data output that can drive the DIN of daisychained slave LCA devices. DOUT data changes on the falling edge of CCLK, 1.5 CCLK periods after it was received at the DIN input. After configuration, DOUT is a user-programmable I/O pins. D0 - D7 During Master Parallel and peripheral configuration modes, these eight input pins receive configuration data. After configuration, they are user-programmable I/O pins. DIN Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-k to 100-k pull-up resistor. 24 R Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature in plastic packages Junction temperature in ceramic packages -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Supply voltage relative to GND VCC Supply voltage relative to GND Supply voltage relative to GND VIHT VILT VIHC VILC TIN Commercial: Industrial: Military: 0C to 70C -40C to 85C -55C to 125C Min 4.75 4.5 4.5 2.0 0 70% 0 Max 5.25 5.5 5.5 VCC 0.8 100% 20% 250 Units V V V V V VCC VCC ns High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time DC Characteristics Over Operating Conditions Symbol VOH VOL ICCO IIL CIN IRIN Description High-level output voltage @ IOH = -8.0 mA, VCC min Low-level output voltage @ IOL = 8.0 mA, VCC max (Note 1) Quiescent LCA supply current (Note 1) Leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) 0.02 -10 Min 3.86 0.4 15 +10 15 0.25 Max Units V V mA A pF mA Note: 1. With no output current loads, all package pins at VCC or GND, and the LCA configured with a MakeBits tie option. 25 XC5200 Logic Cell Array Family Global Buffer Switching Characteristic Guidelines Preliminary Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Global Signal Distribution From pad through global buffer, to any clock (CK) TBUFG XC5202 XC5204 XC5206 XC5210 XC5215 Internal Clock to Output Pad Delay From clock (CK) to output pad (fast), using direct connect between Q and output (O) TOKPOF XC5202 XC5204 XC5206 XC5210 XC5215 From clock (CK) to output pad (slew-limited), using direct connect between Q and output (O) TOKPOS XC5202 XC5204 XC5206 XC5210 XC5215 Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. -6 Max (ns) -5 Max (ns) -4 Max (ns) Symbol Device 9.4 9.4 8.8 8.8 9.9 9.9 8.9 8.9 14.8 14.8 12.7 12.7 26 R Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description TBUF driving a Longline TS I TBUF O -6 Max (ns) -5 Max (ns) -4 Max (ns) Symbol Device I to Longline, while TS is Low; i.e., buffer is constantly active TIO XC5202 XC5204 XC5206 XC5210 XC5215 4.0 4.0 3.6 3.6 TS going Low to Longline going from floating High or Low to active Low or High TON XC5202 XC5204 XC5206 XC5210 XC5215 5.3 5.3 4.8 4.8 TS going High to TBUF going inactive, not driving Longline TOFF XC5202 XC5204 XC5206 XC5210 XC5215 2.4 2.4 2.2 2.2 Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. 27 XC5200 Logic Cell Array Family Guaranteed Input and Output Parameters (Pin-to-Pin) Preliminary All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the Global Buffer specifications. The XACT delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. Speed Grade Description Global Clock to Output Pad (fast) CLB TBUFG Global Clock-to-Output Delay Direct Connect -6 Max (ns) -5 Max (ns) -4 Max (ns) Symbol TICKOF IOB . . . . Device XC5202 XC5204 XC5206 XC5210 XC5215 (Max) FD 17.2 17.2 15.4 15.4 Global Clock to Output Pad (slew-limited) CLB TBUFG Global Clock-to-Output Delay Direct Connect TICKO . . . . XC5202 XC5204 XC5206 XC5210 XC5215 21.7 21.7 19.0 19.0 IOB (Max) FD Input Set-up Time (no delay) to CLB Flip-Flop IOB Input Set-up & Hold Time Direct Connect TPSUF (Min) XC5202 XC5204 XC5206 XC5210 XC5215 1.2 1.2 0.5 0.5 CLB FD TBUFG Input Hold Time (no delay) to CLB Flip-Flop IOB Input Set-up & Hold Time Direct Connect TPHF (Min) XC5202 XC5204 XC5206 XC5210 XC5215 3.0 3.0 2.5 2.5 CLB FD TBUFG Input Set-up Time (with delay) to CLB Flip-Flop IOB Input Set-up & Hold Time Direct Connect TPSU (Min) XC5202 XC5204 XC5206 XC5210 XC5215 7.5 7.5 6.4 6.4 CLB FD TBUFG Input Hold Time (with delay) to CLB Flip-Flop IOB Input Set-up & Hold Time Direct Connect TPH (Min) XC5202 XC5204 XC5206 XC5210 XC5215 0 0 0 0 CLB FD TBUFG Note: 1. 2. 3. These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be used to assure that direct connects are used. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. 28 R IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Input Propagation Delays from CMOS or TTL Levels Pad to I (no delay) Pad to I (with delay) Output Propagation Delays to CMOS or TTL Levels Output (O) to Pad (fast) Output (O) to Pad (slew-limited) 3-state to Pad active (fast) 3-state to Pad active (slew-limited) Internal GTS to Pad active (fast) Internal GTS to Pad active (slew-limited) Note: 1. -6 Max (ns) -5 Max (ns) -4 Max (ns) Symbol TPI TPID 5.4 11.1 4.9 10.2 TOPF TOPS TTSONF TTSONS TGTSF TGTSS 4.6 9.4 6.9 11.6 17.7 22.3 4.5 8.3 6.6 10.4 15.9 19.7 2. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors. 29 XC5200 Logic Cell Array Family CLB Switching Characteristic Guidelines Preliminary Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Combinatorial Delays F inputs to X output DI inputs to DO output (Logic-Cell Feedthrough) F inputs via F5_MUX to DO output Carry Delays Incremental delay per bit Carry-in overhead from DI Carry-in overhead from F Carry-out overhead to DO Sequential Delays Clock (CK) to out (Q) (Flip-Flop) Gate (Latch enable) going active to out (Q) Set-up Time Before Clock (CK) F inputs F inputs via F5_MUX DI input CE input Hold Times After Clock (CK) F inputs F inputs via F5_MUX DI input CE input Clock Widths Clock High Time Clock Low Time Reset Delays Width (High) Delay from CLR to Q (Flip-Flop) Delay from CLR to Q (Latch) Global Reset Delays (see Note 2) Width (High) Delay from internal GCLR to Q Note: 1. 2. -6 Min (ns) Max (ns) 5.5 4.2 7.1 0.7 1.7 3.6 3.9 5.4 8.6 2.1 3.6 0.5 1.2 0 0 0 0 6.0 6.0 6.0 7.3 6.1 6.0 12.4 6.0 1.5 2.7 0.3 0.9 0 0 0 0 6.0 6.0 6.0 Min (ns) -5 Max (ns) 4.5 3.3 5.7 0.6 1.5 3.2 3.1 4.4 6.8 Min (ns) -4 Max (ns) Symbol TILO TIDO TIMO TCY TCYDI TCYL TCYO TCKO TGO TICK TMICK TDICK TEICK TCKI TCKMI TCKDI TCKEI TCH TCL TCLRW TCLR TCLRL TGCLRW TGCLR 5.8 4.8 10.2 The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold-time requirement (TCKDI) of any CLB on the same die. Timing is based upon the XC5210 device. For other devices, see XACT Timing Calculator. 30 R 31 XC5200 Logic Cell Array Family Preliminary (v1.0) Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 R2C1 R2C14 R3C1 R3C14 R4C1 R4C14 R5C1 R5C14 R6C1 R6C14 R7C1 R7C14 Left R8C1 R8C14 Right R9C1 R9C14 R10C1 R10C14 R11C1 R11C14 R12C1 R12C14 R13C1 R13C14 R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 18. XC5206 CLB-to-Pad Relationship 32 R Left 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Bottom Right Top 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 R1C1 R14C1 R1C14 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 R1C1 R2C1 R14C2 R2C14 R1C2 R3C1 R14C3 R3C14 R1C3 R4C1 R14C4 R4C14 R1C4 R5C1 R14C5 R5C14 R1C5 R6C1 R14C6 R6C14 R1C6 R7C1 R14C7 R7C14 R1C7 R8C1 R14C8 R8C14 R1C8 R9C1 R14C9 R9C14 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 R1C9 R10C1 R14C10 R10C14 R1C10 R11C1 R14C11 R11C14 R1C11 R12C1 R14C12 R12C14 R1C12 R13C1 R14C13 R13C14 R1C13 R14C1 R14C14 R14C14 R1C14 130 Note: Pad numbers (1, 2, ..., 148) refer to die pads, not external device pins. Also see the XC5206 pinout table on pages 36-37. Figure 19. XC5206 CLB-to-Pad Relationship (Detail) 33 XC5200 Logic Cell Array Family Preliminary (v1.0) Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18 R2C1 R2C18 R3C1 R3C18 R4C1 R4C18 R5C1 R5C18 R6C1 R6C18 R7C1 R7C18 R8C1 R8C18 R9C1 R9C18 Left R10C1 R10C18 Right R11C1 R11C18 R12C1 R12C18 R13C1 R13C18 R14C1 R14C18 R15C1 R15C18 R16C1 R16C18 R17C1 R17C18 R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 20. XC5210 CLB-to-Pad Relationship 34 R Left 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Bottom Right 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 R9C18 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 R15C18 134 133 132 131 130 129 128 127 126 125 124 Top 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 R1C1 R18C1 R1C18 R1C1 R2C1 R18C2 R2C18 R1C2 R3C1 R18C3 R3C18 R1C3 R4C1 R18C4 R4C18 R1C4 R5C1 R18C5 R5C18 R1C5 R6C1 R18C6 R6C18 R1C6 R7C1 R18C7 R7C18 R1C7 R8C1 R18C8 R8C18 R1C8 R9C1 R18C9 R1C9 R10C1 R18C10 R10C18 R1C10 R11C1 R18C11 R11C18 R1C11 R12C1 R18C12 R12C18 R1C12 R13C1 R18C13 R13C18 R1C13 R14C1 R18C14 R14C18 R1C14 R15C1 R18C15 R1C15 R16C1 R18C16 R16C18 R1C16 R17C1 R18C17 R17C18 R1C17 R18C1 R18C18 R18C18 R1C18 172 Note: Pad numbers (1, 2, ..., 196) refer to die pads, not external device pins. Also see the XC5210 pinout table on pages 38-39. Figure 21. XC5210 CLB-to-Pad Relationship (Detail) 35 XC5200 Logic Cell Array Family Preliminary (v1.0) XC5206 Pinouts Pin Description PC84 PQ160 PQ208 PG191 Boundary Scan Order Pin Description PC84 PQ160 PQ208 PG191 Boundary Scan Order VCC 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND 11. 12. 13. 14. 15. 16. 17. 18. I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O (A15) VCC GND 19. 20. 21. 22. 23. 24. 25. 26. GCK1 (A16, I/O) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 183 184 185 186 187 188 189 190 191 192 193 194 195* 196* 197 198 199 200 201 202 203 204 205 206* 207* 208* 1* 2 3* 4 5 6 7 8 9 10 11 12* 13* 14 15 16 17 18 19 20 21 22 23 24 25 26 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 87 90 93 99 102 105 111 114 117 123 126 129 138 141 150 153 162 165 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 246 249 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND - 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 27 28 29 30 31 32 33 34 35 36 37 38* 39* 40 41 42 43 44 45 46 47 48 49 50 51* 52* 53* 54* 55 56 57 58 59 60 61 62 63 64 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C10 B10 A9 A10 A11 C11 B11 A12 B12 A13 C12 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 G16 E18 F18 G17 G18 H16 H17 H18 J18 J17 J16 J15 K15 K16 255 258 261 267 270 273 279 282 285 291 294 297 303 306 309 315 318 321 330 333 336 339 348 351 354 360 363 372 375 378 384 387 390 396 399 402 408 411 414 420 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O GND 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. I/O I/O I/O (TMS) I/O I/O I/O I/O I/O I/O I/O GND VCC VCC GND 76. I/O * Indicates unconnected package pins. Leading number refers to bonded pad, shown in Figure 19. 36 R XC5206 Pinouts (continued) Pin Description PC84 PQ160 PQ208 PG191 Boundary Scan Order Pin Description PC84 PQ160 PQ208 PG191 Boundary Scan Order 77. 78. 79. 80. 81. 82. 83. 84. 85. I/O I/O I/O I/O I/O I/O I/O I/O I/O GND - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 81 82 83 84 85 86 87 88 89 90 91* 92* 93 94 95 96 97 98 99 100 101 102* 103 104* 105* 106 107* 108 109 110 111 112 113 114 115 116 117* 118* 119 120 121 122 123 124 125 126 127 128 129 130 131 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 V17 V16 T13 U14 T12 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 423 426 432 435 438 444 447 450 456 459 468 471 480 483 486 492 495 504 507 516 519 522 528 531 534 540 543 552 555 558 564 567 570 576 579 - 112. I/O (D3) 113. I/O (RS) 114. I/O 115. I/O 116. I/O 117. I/O 118. I/O (D2) 119. I/O 120. I/O 121. I/O GND 122. I/O 123. I/O 124. I/O (D1) 125. I/O (RCLKBUSY/RDY) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 132 133 134 135 136 137 138 139 140 141 142 143* 144* 145 146 147 148 149 150 151 152 153 154 155* 156* 157* 158* 159 160 161 162 163 164 165 166 167 168 169* 170* 171 172 173 174 175 176 177 178 179 180 181 182 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 M3 P1 N1 M2 M1 L3 L2 L1 K1 K2 K3 K4 588 591 600 603 612 615 618 624 627 630 636 639 642 648 651 654 660 663 9 15 18 21 27 30 33 42 45 51 54 57 63 66 69 75 78 81 - 86. 87. 88. 89. 90. 91. 92. 93. I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG 126. I/O 127. I/O 128. I/O (D0, DIN) 129. I/O (DOUT) CCLK VCC 130. (I/O) TDO GND 131. I/O (A0, WS) 132. I/O (GCK4, A1) 94. 95. 96. 97. 98. 99. I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O 133. I/O 134. I/O 135. I/O (CS1, A2) 136. I/O (A3) 137. I/O 138. I/O GND 139. I/O 140. I/O 141. I/O (A4) 142. I/O (A5) 143. I/O 144. I/O 145. I/O 146. I/O 147. I/O (A6) 148. I/O (A7) GND 100. I/O 101. I/O GND 102. I/O 103. I/O 104. I/O (D5) 105. I/O (CS0) 106. I/O 107. I/O 108. I/O 109. I/O 110. I/O (D4) 111. I/O VCC GND Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 666 = BSCAN.UPD 37 XC5200 Logic Cell Array Family Preliminary (v1.0) XC5210 Pinouts Pin Description PC84 Boundary PQ160 PQ208 PG223 PQ240 Scan Order Pin Description PC84 Boundary PQ160 PQ208 PG223 PQ240 Scan Order 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206* 207* 208* 1* 2 3* 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 J4 J3 J2 J1 H1 H2 H3 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10 212 213 214 215 216 217 218 219* 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22* 23 24 25 26 27 28 29 30 31 111 114 117 123 126 129 135 138 141 150 153 162 165 171 174 177 183 186 189 195 198 201 210 213 222 225 231 234 237 243 246 249 255 258 261 267 270 273 279 282 285 291 294 297 306 309 318 321 327 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND 100. I/O 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51* 52* 53* 54* 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 G15 H15 H18 J18 J17 J16 J15 K15 K16 32 33 34 35 36 37* 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83* 84 85 86 87 88 89 90 91 92 330 333 339 342 345 351 354 357 363 366 369 375 378 381 387 390 393 399 402 405 411 414 417 426 429 432 435 444 447 450 456 459 462 468 471 474 480 483 486 492 495 504 507 510 516 519 522 528 531 534 540 * Indicates unconnected package pins. Leading number refers to bonded pad, shown in Figure 21. 38 R XC5210 Pinouts (continued) Pin Description PC84 Boundary PQ160 PQ208 PG223 PQ240 Scan Order Pin Description PC84 Boundary PQ160 PQ208 PG223 PQ240 Scan Order 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. 148. I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102* 103 104* 105* 106 107* 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 93 94 95 96 97 98* 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143* 144 145 146 147 148 149 150 151 152 543 546 552 555 558 564 567 570 576 579 588 591 600 603 606 612 615 618 624 627 630 636 639 648 651 660 663 666 672 675 678 684 687 690 696 699 708 711 714 720 723 726 732 735 738 744 747 756 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. I/O (RCLKBUSY/RDY) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155* 156* 157* 158* 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 U9 V9 V8 U8 T8 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P4 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 153 154 155 156 157 158* 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195* 196 197 198 199 200 201 202 203 204* 205 206 207 208 209 210 211 759 768 771 780 783 786 792 795 798 804 807 810 816 819 822 828 831 834 840 843 846 855 858 9 15 18 21 27 30 33 39 42 45 51 54 57 66 69 75 78 81 87 90 93 99 102 105 - I/O (DOUT) CCLK VCC 172. I/O (TDO) GND 173. I/O (A0, WS) 174. GCK4 (I/O, A1) 175. I/O 176. I/O 177. I/O (CS1, A2) 178. I/O (A3) 179. I/O 180. I/O 181. I/O 182. I/O 183. I/O 184. I/O GND 185. I/O 186. I/O 187. I/O 188. I/O VCC 189. I/O (A4) 190. I/O (A5) 191. I/O 192. I/O 193. I/O 194. I/O 195. I/O (A6) 196. I/O (A7) GND 168. 169. 170. 171. I/O I/O I/O (D0, DIN) Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 666 = BSCAN.UPD 39 XC5200 Logic Cell Array Family Preliminary (v1.0) Physical Dimensions 0.045 x 45 11 12 1 Pin 1 ID 75 74 1.190 0.005 1.154 0.004 32 33 Dimensions in Inches Lead Pitch 50 Mil 0.175 0.010 1.154 0.004 1.190 0.005 Top View 0.028 53 54 0.045 0.045 0.004 -C- 0.100 0.010 0.017 1.000 Typ 1.120 0.010 Side View X3426 0.020 84-Pin Plastic PLCC (PC84) 31.20 Sq 28.00 Sq 120 121 81 -C- 0.10 80 0.28 0.05 5- 7 160 Pin 1 ID 1 Top View Dimensions in Millimeters Lead Pitch 0.65 mm 40 3.38 0.20 Stand-Off 0.10-0.36 X3434 41 Side View 160-Pin Plastic PQFP (PQ160) 40 R 0.100 Typ V U 0.070 Dia Typ (191 Places) T R P N M L K J H G F E Stand-Off Pin (4 Places) D C B A 0.050 X 45 Pin #1 Side S/R 0.890 Sq 1.860 0.019 Sq 1.700 Typ Top Edge Chamfer 0.010 X 45 Typ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Dielectric Coat Bottom View 0.050 0.010 Chamfer 0.030 0.010 X 45 (3 Places) Top View Gold Plate Pin #1 Index Top Side 0.090 0.010 0.008 (4 Places) 0.050 X 0.025 0.018 0.002 Au Plated Kovar Side View 0.005 R Typ Dimensions in Inches 0.130 0.010 X3438 191-Pin Ceramic PGA (PG191) 30.60 Sq 28.00 Sq 156 105 -C- 0.08 157 104 0.13 0.25 12 - 16 208 Pin 1 ID 1 Top View Dimensions in Millimeters Lead Pitch 0.50 Side View 52 0.064 Ref 3.67 3.17 Stand-Off 0.25 Min X3439 53 208-Pin Plastic PQFP (PQ208) 41 XC5200 Logic Cell Array Family Preliminary (v1.0) 0.100 Typ V U T R P N M L K J H G F E D C B A S/R 0.899 Max Sq 0.070 Dia Typ (223 Places) 1.860 0.019 Sq 1.700 Typ Stand-Off Pin (4 Places) Top Edge Chamfer 0.010 X 45 TYP 0.050 X 45 Pin #1 Side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Dielectric Coat Bottom View 0.050 0.010 Chamfer 0.030 0.010 X 45 (3 Places) 0.090-0.110 Top View Gold Plate Pin #1 Index Top Side 0.008 (4 Places) 0.050 X 0.025 Dimensions in Inches 0.018 0.002 Au Plated Kovar Side View 0.005 R Typ 0.130 0.010 X3441 223-Pin Ceramic PGA (PG223) Pin 1 ID #1Pin 240 181 180 32.00 34.60 0.020 Typ 60 61 Top View 12-16 (2 Halves) 3.50 3.30 0.14-0.30 120 121 Dimensions in Millimeters Lead Pitch 0.50 mm 0.10 Side View -C- X3442 Stand-Off 0.25 Min 240-Pin Plastic PQFP (PQ240) 42 R Ordering Information Example: Device Type Speed Grade XC5210-6PQ208C Temperature Range Number of Pins Package Type Component Availability PINS TYPE CODE -7 XC5206 -6 -5 -7 XC5210 -6 -5 84 PLASTIC PLCC PC84 CI CI C CI CI CI 160 PLASTIC PQFP PQ160 CI CI C CI CI CI 191 CERAMIC PGA PG191 CI CI C 208 PLASTIC PQFP PQ208 CI CI C CI CI CI 223 CERAMIC PGA PG223 240 PLASTIC PQFP PQ240 CI CI CI CI CI CI C = Commercial = 0 to +70C I = Industrial = -40 to +85C Number of Available I/O Pins Package Type Device XC5206 XC5210 Max I/O 148 196 PC84 65 65 PQ160 133 133 PG191 148 PQ208 148 164 196 196 PG223 PQ240 43 R The Programmable Logic Company SM 2100 Logic Drive, San Jose CA 95124-3400 Tel: (408) 559-7778 FAX: (408) 559-7114 0401300 Printed in U.S.A. P/N 0401300 E2 |
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